Coding equipment providing compressed code

ABSTRACT

In a parallel digital signal delivered from an AD converter, &#34;1&#34; appearing in a bit position nearest to the most significant digit (MSD) is detected, and the parallel digital signal is converted into a serial digital signal consisting of a weight character indicating this specific bit position and a data character indicating the numerical value of the data. Further, a weight bit is provided for changing the weight of the output of the AD converter depending on the analog quantity subjected to AD conversion so as to reduce the number of bits required for coding the parallel signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a coding equipment for converting a paralleldigital signal into a serial digital signal.

2. Description of the Prior Art

It is commonly known that, in a centralized control of physicalquantities such as voltage, current and temperature measured at remotepoints, these physical quantities are sampled with a suitable period atthe individual measuring points, and after converting the respectivesampled physical quantities into parallel digital signals by ananalog-digital converter, these parallel digital signals are convertedinto a succession of serial digital signals to be transmitted to acentral control station. In this case, in order that the informationprocessing, storing and other operations in the central control stationcan be efficiently carried out, it is required that the informationtransmitted one after another in the form of the serial digital signalhave the same number of bits regardless of the magnitude of the absolutevalue of the physical quantities sampled periodically. On the otherhand, however, the fact that the information transmitted one afteranother in the form of the serial digital signal have the same number ofbits means that the greatest value of each information is also limitedto a predetermined number of bits even when great variations occur inthe physical quantities. Thus, the magnitude of the physical quantitycorresponding to the least significant digit (LSD) is inevitablyincreased resulting frequently in a great error when the physicalquantity is small.

In an effort to obviate the above defect, a proposal is made in, forexample, U.S. Pat. No. 3,298,016 in which the magnitude of a physicalquantity is coded as a combination of a numerical value of apredetermined number of digits making possible to express the numericalvalue by a predetermined number of bits and an index representing thelargeness of the numerical value. This proposal is effective from thestandpoint that physical quantities are converted into signals of thesame number of bits and can be coded with high precision. However, themeans disclosed in this proposal cannot be utilized when a fully digitalunit is desired due to the fact that means for handling an analogquantity is included therein.

SUMMARY OF THE INVENTION

It is therefore a primary object of the present invention to provide acoding equipment in which a parallel digital signal can be convertedinto a serial digital signal of predetermined number of bits withouthandling any analog quantity.

According to the present invention, the bit position of the mostsignificant digit (MSD) in a parallel digital signal corresponding to aphysical quantity is detected and coding is controlled depending on thisbit position so that the physical quantity can be coded with highprecision in a fully digital fashion.

BRIEF DESCRIPTION OF THE DRAWING

FIGS. 1a and 1b illustrate errors occurring during AD conversion.

FIG. 2 shows a manner of information transmission according to thepresent invention.

FIG. 3 is a block diagram of a typical embodiment of the presentinvention.

FIG. 4 shows the detailed structure of the block 5 in FIG. 3.

FIG. 5 shows the detailed structure of the block 6 in FIG. 3.

FIGS. 6a and 6b show the detailed structure of the block 7 in FIG. 3.

FIGS. 7a and 7b are time charts illustrating the operation of theembodiment of the present invention.

FIG. 8 shows a manner of AD conversion conveniently used in the practiceof the present invention.

FIG. 9 is a block diagram of an AD converter based on the principleshown in FIG. 8.

FIGS. 10 and 11 are views similar to FIGS. 3 and 2 respectively butshowing another embodiment which employs the AD converter shown in FIG.9.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention will be described in detail with reference to anapplication in which a physical quantity sampled with a predeterminedperiod is subjected to analog-digital conversion for measurement.

When physical quantities are measured and the measured quantities aretransmitted in large amounts, a digital signal transmission system isgenerally employed in view of the advantages from the standpoints of therequired frequency band and information processing, storing and otheroperations in a receiving station. In this system, therefore, ananalog-digital converter is disposed in the transmitting station forconverting various analog values measured at measuring points intodigital quantities, and then the digital quantities are arranged in theform of a series signal to be transmitted to the receiving station. Inthis case, the maximum value of the error due to the AD conversion isgiven by ±1/2 of the least significant digit (LSD). Therefore, when thefull scale of the AD converter is N, the maximum value of the error isgiven by ±1/2· (1/2^(N)), and the error ε due to the AD conversion isgenerally expressed as follows: ##EQU1##

This relation is shown in FIG. 1a in which the horizontal axisrepresents the scale N and the vertical axis represents the error ε. Itwill be seen that the error ε is ε₁ when N= N₁, and this error ε is ε₂(ε₂ < ε₁) when N= N₂ (N₂ > N₁). Thus, the error ε is reduced with theincrease in the scale N.

On the other hand, the maximum value I_(MAX) and minimum value I_(MIN)of the analog input I are determined depending on the transmissionsystem. In order that the conversion error ε of the AD converter can belimited to lower than an allowable maximum error ε_(MAX) allowable forthe specific system, these values must be selected to satisfy thefollowing relation (2) which is a severest condition: ##EQU2##

FIG. 1b shows the relation between the error ε and the analog input Iselected to satisfy the inequality (2). It is apparent from FIG. 1bthat, when the inequality (2) is satisfied, the minimum error ε_(MIN)corresponding to I_(MAX) is included with a sufficient margin within therange of the allowable maximum error ε_(MAX).

A digital transmission system for measured quantities is designed sothat each individual measured quantity is expressed in the form of Nbits determined by the full scale N of the AD converter regardless ofthe margin of the input I relative to the allowable maximum errorε_(MAX) as shown in FIG. 1b. This system has been significant in that acompact and standardized structure can be provided for the hardwareprocessing the transmitted and received measured quantity, but thissystem has not necessarily been most suitable from the viewpoint of theefficiency of transmission.

The present invention provides a practically useful coding equipmentwhich retains the merit of capability of standardization of thetransmitted and received information processing hardware in the digitaltransmission system of the kind above described and yet which provides agreat improvement in the transmission efficiency which has been thedemerit of the prior art system.

More precisely, in the transmission of the parallel digital signal whichare the output appearing after the AD conversion, the present inventionutilizes positively the fact that the margin of the conversion error εin the output value relative to the allowable maximum error ε_(MAX)allowable for the specific transmission system varies greatly dependingon the magnitude of the analog input I as shown by the inequality (2)and in FIG. 1b. According to the present invention, the margin of theerror is uniformly distributed as far as possible for all the ADconverter outputs so that, when the input has a large value, the numberof bits transmitted can be reduced by the amount corresponding to themargin of the error.

The manner of reducing the number of bits according to the presentinvention will now be described. In the transmission of a binaryinformation output of an AD converter having a scale of N bits, thedigit corresponding to the maximum level of the value obtained bysampling of the information, (that is, "1" nearest to the MSD in the ADconverted output when the output is expressed in the form of binaryinformation) is employed as the MSD of the information to betransmitted, and this digit is called hereinafter a TMSD fordistinguishing same from the term MSD commonly employed. A datacharacter DC of X bits following the TMSD and a weight character WC of Ybits representing the weight of the TMSD are solely transmitted. Inorder that the error ε in all the sampled and transmitted informationmay not exceed the allowable limit ε_(MAX), X and Y may be selected asfollows: ##EQU3##

When the TMSD is situated in the position spaced by K bits (K< N) fromthe LSD of the AD converter output, X in the transmitted informationmust satisfy the allowable maximum error ε_(MAX). From the abovecondition, the following relation holds: ##EQU4## By solving theinequality (5), X satisfying the above condition can be sought from theinequality (3). Further, the number of bits Y required for indicatingthe weight of the TMSD is given by the following inequality:

    2.sup.Y ≧ N- K                                      (6)

since ##EQU5## in the numerator and denominator of the inequality (5) isa finite geometric series, this can be expressed as ##EQU6## Practicalnumerical values will now be considered for ease of understanding. When,for example, N and K are supposed to be n= 12 and K= 6 and ε_(MAX) istaken as a parameter, X and Y are sought from the inequalities (3) and(4) as shown in Table 1.

                  Table 1                                                         ______________________________________                                                            Required number of                                                                        bits transmitted =                            Case                            integer of X and                              No.    ε.sub.MAX                                                                      X        Y      integer of Y                                  ______________________________________                                        1      0.01     6.28     2.59   10                                            2      0.02     5.80     2.59   9                                             3      0.03     5.42     2.59   9                                             4      0.04     5.13     2.59   9                                             5      0.05     4.88     2.59   8                                             ______________________________________                                    

From Table 1, it is apparent that the number of bits X+ Y required forinformation transmission is 10 in the case No. 1, 9 in the cases Nos. 2to 4, and 8 in the case No. 5. Thus, it is apparent that the number ofbits is less by 2 bits in the case No. 1, by 3 bits in the cases Nos. 2to 4, and by 4 bits in the case No. 5 than when the full scale N= 12bits of the AD converter is transmitted within the range of theallowable maximum error ε_(MAX). It will thus be understood that themethod above described is very effective in improving the efficiency oftransmission.

The present invention has a great significance in that a practicalcoding equipment is proposed in which conversion based on theinequalities (3) and (4) is carried out by digital means described laterso that the number of bits transmitted can be reduced to a minimumwithin the range of the allowable maximum error ε_(MAX) allowable for aspecific transmission system. In the present invention too, it isapparent that standardization of the transmitted and receivedinformation processing hardware can be attained as heretofore due to thefact that individual measured values are naturally transmitted in theform of binary information of equal bit length.

As a typical example, the present invention will be described withreference to an application to a transmission system in which ADconverted data are arranged in series in the order of D1, D2 . . . . Dmas shown in FIG. 2 and such data signals are cyclically transmitted. Thescale N and allowable maximum error ε_(MAX) may be those determineddepending on the transmission system. It is assumed herein that thescale N= 12 and the allowable maximum error ε_(MAX) = 0.02. Since thiscorresponds to the case No. 2 shown in Table 1, the numbers of bits Xand Y required for transmission are X= 6 and Y= 3. In actualtransmission, one parity bit P is added to these bits X and Y to give atotal of 10 bits. As shown in FIG. 2, the weight character WC of Y= 3bits starts from the MSD and is followed by the data character DC of X=6 bits which starts from the TMSD, and the data character DC is followedby the parity portion of P= 1 bit.

FIG. 3 is a block diagram showing a typical structure of a measured datatransmitting equipment in an embodiment of the present invention.Referring to FIG. 3, the block 2 designates a timing control circuitwhich is connected to a clock pulse generator 1 and applies timingpulses to various parts of the equipment for regulating the operation ofthese parts. The block 3 designates an AD converter having a scale of N=12 bits. The block 4 designates a 12-bit buffer register for temporarilystoring therein the AD converted measured data before transmission. Theblock 5 designates a transfer control instruction circuit which detectsthe position of the TMSD in the data information stored in the bufferregister 4 and applies instruction signals to a transfer gate 7 andweight character coding circuit 6 (described below) so as to instructthe portion of X= 6 bits to be selected from the data information fortransfer and to instruct the construction of the weight character WC.The block 6 designates a circuit for coding the weight character WC inresponse to the instruction signal applied from the transfer controlinstruction circuit 5. The block 7 designates a data transfer gatewhich, in response to the application of the instruction signal from thetransfer control instruction circuit 5, transfers the portion of X= 6bits starting from the TMSD in the data information stored in the bufferregister 4 to a PS converter (described below) as the data bits to betransmitted. The block 8 designates a PS converter which, in response tothe application of the timing pulses from the timing control circuit 2,receives the signals applied in parallel from the weight charactercoding circuit 6 and data transfer gate 7 and arranges such signals in aserial signal as shown in FIG. 2. The blocks 9 and 10 designate a paritygeneration circuit and a synchronizing signal generation circuitrespectively which are connected to an OR gate 11.

The data information is applied to the AD converter 3 from an inputterminal A, and the serial signal appears from an output terminal B ofthe OR gate 11, this output terminal B being the output terminal of thetransmitting equipment. An AD conversion instruction pulse signal isapplied from the timing control circuit 2 to the AD converter 3 by aline TAD. A write instruction pulse signal is applied from the timingcontrol circuit 2 to the buffer register 4 by a line TBR for instructingthe writing of the output of the AD converter 3 in the buffer register4. A timing regulation instruction pulse signal is applied from thetiming control circuit 2 to the PS converter 8 by nine lines TM1 to TM9provided for individual digits. A parity generation timing regulationinstruction signal is applied from the timing control circuit 2 to theparity generation circuit 9 by a line TM10. Twelve lines 300 to 311, onefor each digit, are provided for applying the output of the AD converter3 to the buffer register 4. Twelve lines 400 to 411 are provided fortransferring the output of the buffer register 4 to the transfer controlinstruction circuit 5 and the data transfer gate 7. Seven lines 505 to511 are provided for applying the transfer control instruction pulsesignal to the weight character coding circuit 6 and data transfer gate7. Three lines 600 to 602 are provided for applying the coded weightcharacter WC of Y= 3 bits to the PS converter 8. Six lines 700 to 705are provided for applying the data character DC of X= 6 bits startingfrom the TMSD to the PS converter 8. A synchronizing signal additiontiming regulation instruction pulse signal is applied from the timingcontrol circuit 2 to the synchronizing signal generation circuit 10 by aline TSYC.

The clock pulse generator 1, timing control circuit 2, AD converter 3,buffer register 4, PS converter 8, parity generation circuit 9 andsynchronizing signal generation circuit 10 in the embodiment of thepresent invention shown in FIG. 3 may be conventional ones, andtherefore, any detailed description of the structure of these parts isunnecessary.

The present invention is featured by the fact that the transfer controlinstruction circuit 5, weight character coding circuit 6 and datatransfer gate 7 are disposed between the buffer register 4 and the PSconverter 8 so as to reduce the number of bits transmitted by thesystem. Therefore, the embodiment of the present invention will bedescribed while placing emphasis on the structure and operation of theseparts.

The structure of the transfer control instruction circuit 5 will bedescribed at first. This circuit 5 detects the position of the TMSD inthe data information written in the buffer register 4 and informs theweight character coding circuit 6 and data transfer gate 7 of thedetected position of the TMSD. To this end, the transfer controlinstruction circuit 5 must have a structure which satisfies thecondition described below. That is, whether the position of the TMSD inthe buffer register 4 lies in the bit position 2¹¹, bit position 2¹⁰,bit position 2⁹, bit position 2⁸, bit position 2⁷, bit position 2⁶ orbit positions ranging from 2⁵ to 2⁰ must be detected. Therefore, thetransfer control instruction circuit 5 satisfying the above conditionmay have a structure as shown in FIG. 4.

Referring to FIG. 4, the transfer control instruction circuit 5 includesa plurality of INHIBIT gates 51 to 55, an OR gate 56 and a phaseinverting gate 57. A signal of "1" level is applied to this transfercontrol instruction circuit 5 by the lines 411, 410, 409, 408, 407 and406 when the TMSD in the data in the buffer register 4 lies in the bitpositions 2¹¹, 2¹⁰, 2⁹, 2⁸, 2⁷ and 2⁶ respectively. It can be seentherefore that the TMSD lies in one of the bit positions ranging from 2⁵to 2⁰ when the signal of "1" level does not appear in anyone of theselines 411 to 406. An output signal of "1" level is applied to the weightcharacter coding circuit 6 and data transfer gate 7 by the lines 511,510, 509, 508, 507, 506 and 505 when the TMSD is detected to lie in thebit position 2¹¹, bit position 2¹⁰, bit position 2⁹, bit position 2⁸,bit position 2.sup. 7, bit position 2⁶ and bit positions 2⁵ to 2⁰respectively, so as to instruct the transfer control of signals appliedfrom the weight character coding circuit 6 and data transfer gate 7 tothe PS converter 8.

The weight character coding circuit 6 acts to code the weight characterWC of Y= 3 bits which is added to the data character DC to indicate theweight of the TMSD in the data character DC to be transmitted, that is,the position of the TMSD in the AD converted data of N= 12 bits. Thus,the weight character coding circuit 6 may be constructed to satisfy thecondition described below. That is, the weight character coding circuit6 may deliver "110" when the TMSD detected by the transfer controlinstruction circuit 5 lies in the bit position 2¹¹, hence when theoutput signal of "1" level appears on the line 511. In other words, theweight character coding circuit 6 may apply a signal of "1" level, asignal of "1" level and a signal of "0" level to the PS converter 8 bythe lines 602, 601 and 600 respectively. Similarly, the weight charactercoding circuit 6 may deliver "101" when the detected TMSD lies in thebit position 2¹⁰, hence when the signal of "1" level appears on the line510, "100 " when the detected TMSD lies in the bit position 2⁹, hencewhen the signal of "1" level appears on the line 509, "011" when thedetected TMSD lies in the bit position 2⁸, hence when the signal of "1"level appears on the line 508, "010" when the detected TMSD lies in thebit position 2⁷, hence when the signal of "1" level appears on the line507, "001" when the detected TMSD lies in the bit position 2⁶, hencewhen the signal of "1" level appears on the line 506, and "000" when thedetected TMSD lies in one of the bit positions 2⁵ to 2⁰, hence when thesignal of "1" level appears on the line 505. The respective outputsignals are applied by the lines 602 to 600 to the PS converter 8.Therefore, the weight character coding circuit 6 may have a structure asshown in FIG. 5.

Referring to FIG. 5, the weight character coding circuit 6 includes aplurality of OR gates 61 to 66, and a plurality of INHIBIT gates 67 to69. The input is applied by the lines 505 to 511 and the output isdelivered by the lines 600 to 602. The OR gates 62, 64, 66 and INHIBITgates 67, 68, 69 are not necessarily required due to the fact that theinput signal of "1" level appears generally on only one of the lines 505to 511.

The function of the data transfer gate 7 is such that, in response tothe instruction signal applied from the transfer control instructioncircuit 5, the data character DC of X= 6 bits starting from the TMSD inthe sampled and AD converted data information written in the bufferregister 4 is applied to the PS converter 8. Thus, the data transfergate 7 must be constructed to respond to the instruction signal appliedfrom the transfer control instruction circuit 5. That is, when the TMSDdetected by the transfer control instruction circuit 5 lies in the bitposition 2¹¹, hence when the signal of "1" level appears on the line511, the 6-bit data information ranging from 2¹¹ to 2⁶ in the bufferregister 4 may be applied to the PS converter 8 by the lines 705 to 700in the sequential order starting from the TMSD. Similarly, the 6-bitdata information ranging from 2¹⁰ to 2⁵ may be applied to the PSconverter 8 by the lines 705 to 700 when the detected TMSD lies in thebit position 2.sup. 10, hence when the signal of "1" level appears onthe line 510, the 6-bit data information ranging from 2⁹ to 2⁴ when thedetected TMSD lies in the bit position 2⁹, hence when the signal of "1"level appears on the line 509, the 6-bit data information ranging from2⁸ to 2³ when the detected TMSD lies in the bit position 2⁸, hence whenthe signal of "1" level appears on the line 508, the 6-bit datainformation ranging from 2⁷ to 2² when the detected TMSD lies in the bitposition 2⁷, hence when the signal of "1" level appears on the line 507,the 6-bit data information ranging from 2⁶ to 2¹ when the detected TMSDlies in the bit position 2⁶, hence when the signal of "1" appears on theline 506, and the 6-bit data information ranging from 2⁵ to 2⁰ when thedetected TMSD lies in one of the bit positions 2⁵ to 2⁰ , hence when thesignal of "1" level appears on the line 505. Therefore, the datatransfer gate 7 may have a structure as shown in FIGS. 6a and 6b.

Referring to FIG. 6a, the data transfer gate 7 is composed of six blocks7A to 7F each of which has a structure 70 as shown in detail in FIG. 6b.Referring to FIG. 6b, the block 70 includes a plurality of AND gates 71to 77 and an OR gate 78 to which the outputs of these AND gates 71 to 77are applied. Input lines a, b, c, d, e, f and g of each of the blocks 7Ato 7F shown in FIG. 6a must be connected to the corresponding sevenlines among the lines 400 to 411. Further, an output line h of the block70 shown in FIG. 6b must be connected to the corresponding line amongthe lines 700 to 705 as shown in FIG. 6a.

It is apparent that the reduction in the number of bits describedpreviously can be realized by the provision of the parts havingstructures as above described. The PS converter 8 which provides aseries signal on the basis of input signals may have a structurecommonly known in the art.

FIGS. 7a and 7b are time charts showing the waveform of timingregulating pulses applied from the timing control circuit 2 during thisPS conversion and showing the manner of providing a serial signal. Asshown in FIG. 7a, an AD conversion instruction pulse TAD appears whenthe timing signal TM10 is in the "1" level, and a write instructionpulse TBR for writing the output of the AD converter 3 in the bufferregister 4 appears also when the timing signal TM10 is in the "1" level,but the pulse TBR appears after the disappearance of the pulse TAD.Thus, by use of timing regulating pulses TM1 to TM10 for regulating thetiming of the individual digits, the lth data D(l) starting from timeI(l) and the (l+ 1)th data D(l++ 1) starting from time T(l+ 1) can bearranged in a serial signal.

The generation of the parity bit P is carried out in the block 9 in FIG.3 in response to the application of the timing signal TM10. Further, thegeneration of the synchronizing signal SYC is carried out in the block10 in FIG. 3 in response to the application of a timing signal TSYC asshown in FIG. 7b. In this manner, a data signal as shown in FIG. 7b canbe sent out from the output terminal B in FIG. 3 toward a receivingstation. A modulator (not shown) may be connected to the output terminalB so that the output signal may be transmitted to the receiving stationafter being subjected to high frequency modulation.

It is apparent from the foregoing description of a typical embodiment ofthe present invention that the objects of the present invention can becompletely attained and the desired practical effects can also beexhibited.

While the embodiment of the present invention has been described withreference to cyclic transmission, it is readily apparent from theforegoing description that the present invention is applicable also toother forms of transmission. Further, the present invention provides agreat flexibility due to the fact that the number of required bits ofdata can be sought from the inequalities (3) and (4) on the basis of thecondition given by a specific transmission system. Further, as a matterof course, the desired reduction in the number of bits can also beattained when the blocks 5, 6 and 7 are used as input converting meansin a display circuit and a conventional data processing unit in additionto the use as means for data transmission.

In the embodiment above described, AD converted information including adata character DC of X= 6 bits starting from the TMSD, a weightcharacter WC of Y= 3 bits indicating the weight of the TMDS and a parityP of 1 bit is transmitted in a form as shown in FIG. 2 and all theoutputs of the AD converter have a margin distributed as equally aspossible for the allowable maximum error ε_(MAX) so as to realize thedesired reduction in the number of bits to be transmitted. In anapplication of the present invention, another bit can be reduced under acertain limited condition.

This is limited to the case in which the number of coded forms of theweight character WC (corresponding to the number of TMSD positions to bedetected) has a margin for the value of Y sought from the inequality(4). Under such a condition, information as to whether the TMSD is "1"or "0" 0 can be coded by utilizing the margin in the weight characterWC.

For example, in the case of the embodiment above described, Y= 3 bitsand the weight character WC can be coded in eight forms, while thenumber of TMSD positions to be detected is seven since the number ofbits of X sought from the inequality (3) is X= 6 and the TMSD in the bitposition 2¹¹, bit position 2¹⁰, bit position 2⁹, bit position 2⁸, bitposition 2⁷, bit position 2⁶ and bit positions 2⁵ to 2⁰ is detected.Thus, the former is more than the latter by one. This may be utilized soas to detect the TMSD in the bit position 2⁵ and bit positions 2⁴ to 2⁰and to code this TMSD position by a separate weight character. In such acase, it is apparent that all the data can be correctly decoded in thereceiving station even when the bit portion 2^(X) ⁻¹ in FIG. 2corresponding to the TMSD in the data character DC may be omitted. Thus,the data information transmitted is composed of a total of 9 bitsconsisting of Y= 3 bits, X= 5 bits and P= 1 bit, and the number of bitstransmitted is less than in the above embodiment by one.

It can be known from the above description that the coding equipmentaccording to the present invention can reduce the number of bits in aserial digital signal when a parallel digital signal representing aphysical quantity are produced from the AD converter. The AD converter 3shown in FIG. 3 may be suitably modified for move effective applicationsas will be described below.

An error is naturally involved in the quantization of a measuredquantity as described with reference to FIGS. 1a and 1b. A suitablevalue I_(D) intermediate between a maximum I_(MAX) and a minimum I_(MIN)of a measured quantity I_(i) is selected as shown in FIG. 8, and a valuebetween I_(MAX) and I_(D) and a value between I_(D) and I_(MIN) areconverted by an AD converter to give the same number of bits. The outputof the AD converter includes also a weight bit which indicates the factthat the measured value lies in one of the two ranges above described.This is more effective for the reduction of the number of bitstransmitted. This idea will be described by taking an AD converter ofsuccessive approximation type as an example.

According to this idea, the level of an analog input to be AD convertedis compared with a reference value I_(D) calculated on the basis of anallowable error ε_(AL) of the entire system and the input is quantizedinto a digital signal of q bits, but the weight is different dependingon whether the input level is larger or smaller than the reference valueI_(D). More concretely, in this case, the AD converter delivers adigital output as described below depending on the level of the inputI_(i).

     (1)  I.sub.i ≧ I.sup.D

weight bit WB-- "1"

Data bits-- 2^(q-1), 2^(q-2), . . . 2¹, 2⁰

The input falling within the range of I_(D) to I_(MAX) is AD convertedso that the allowable error of I_(D) is less than ε_(AL).

     (2) i.sub.i < I.sub.D

weight bit WB-- "0"

Data bits-- 2^(q) ⁻ 1, 2^(q) ⁻², . . . 2¹, 2⁰

The input falling within the range of I_(MIN) to I_(D) is AD convertedso that the allowable error of I_(MIN) is less than ε_(MAX).

In this case, therefore, it is important to select the value of I_(D) soas to obtain a satisfactorily balanced AD converter. When the value ofI_(D) is properly selected, the input I_(i) and the AD conversion errorε have a relation as shown in FIG. 8 so that the AD conversion errorincluded in the allowable error of the entire system can be suitablydistributed and the number of bits converted can be reduced by an amountcorresponding to the distribution of the error.

Now, I_(D) and q will be computed supposing that I_(MAX) = 14100 A,I_(MIN) = 100 A, ε_(MAX--) ≦ ± 0.3 and ε_(AL--) ≦ ± 0.04. In the ADconversion in which the weight bit WB is "0" , the severest conditionfor the inequality (2) must be satisfied in order that the conversionerror is less than the allowable error ε_(MAX) shown in FIG. 8. That is,the following relation must hold since I_(MAX) in this case correspondsto I_(D) : ##EQU7## The numerator in the left-hand member in theinequality (8) can be expressed as ±1/2 · I_(LSD1) because ##EQU8##where I_(LSD1) is the weight of the least significant digit (LSD) of thequantized value. Thus, the inequality (8) can be expressed as ##EQU9##From this inequality (9), the weight I_(LSD1) of the least significantdigit is given by

    I.sub.LSD1 < 2· I.sub.MIN · ε.sub.MAX (10)

it is known from the inequality (10) that I_(LSD1) may be selected tosatisfy the value I_(LSD1) < 60 when the values of I_(MIN) = 100 A andε_(MAX) = 0.3 are put in the inequality (10). In view of the arrangementof the quantized bits in the AD converter, it is desirable to select asuitable value of I_(LSD1) which satisfies the above condition in whichI_(MIN) is selected to be I_(MIN) = 100 A. That is, it is desirable toselect a value of I_(LSD1) to be

    I.sub.LSD1 = 100 · (1/2).sup.1 = 50< 60 A.

therefore, the arrangement of bits when the weight bit WB= "0" isdetermined as shown in Table 2.

                  Table 2                                                         ______________________________________                                                   Corresponding analog                                               Digit      quantity                                                           ______________________________________                                        2.sup.7    6400                                                               2.sup.6    3200                                                               2.sup.5    1600                                                               2.sup.4     800                                                               2.sup.3     400                                                               2.sup.2     200                                                               2.sup.1     100                                                               2.sup.0    50                                                                 ______________________________________                                    

However, the bit position of (I_(D) /2) cannot yet be determined fromthe above condition.

In order that the AD conversion error be less than the allowable errorε_(AL) shown in FIG. 8, when the weight bit WB is "1" , the relation##EQU10## must be satisfied since I_(D) in this case corresponds toI_(MIN) in the inequality (2). The numerator in the left-hand member inthe inequality (11) can be expressed as ±1/2· I_(LSD2) where I_(LSD2) isthe weight of the least significant digit of the quantized value. Thus,the inequality (11) can be expressed as ##EQU11## From the inequality(12), I_(LSD2) is given by

    I.sub.LSD2 ≦ 2·I.sub.D ·ε.sub.AL (13)

the value of I_(D) relative to I_(MIN) = 100 is selected to be I_(D) =12800, and this value and the value of ε_(AL) = 0.04 are put in theinequality (13). It is known that I_(LSD2) is selected to satisfy therelation I_(LSD2) ≦ 1024. This I_(LSD2) is also desirably selected to besimilar to one in the bit arrangement obtained when the weight bit WB is"0" or the value of I_(LSD2) is desirably selected from the numberswhich are obtained by multiplying the numbers in the right-hand columnof Table 2 above described. Suppose that the value of I_(LSD2)satisfying these conditions is I_(LSD2) = 800, then the bit arrangementwhen the weight bit WB is "1" is as shown in Table 3.

                  Table 3                                                         ______________________________________                                                   Corresponding analog                                               Digit      quantity                                                           ______________________________________                                        2.sup.7     102400                                                            2.sup.6    51200                                                              2.sup.5    25600                                                              2.sup.4    12800                                                              2.sup.3     6400                                                              2.sup.2     3200                                                              2.sup.1     1600                                                              2.sup.0     800                                                               ______________________________________                                    

It will be seen that these values are well balanced with those in thecase in which the weight bit WB is "0" , and I_(D) = 12800 is anappropriate value. Therefore, the bit arrangement in this case isfinally determined from Table 4.

                                      Table 4                                     __________________________________________________________________________     Digit                                                                              WB 2.sup.7                                                                           2.sup.6                                                                           2.sup.5                                                                           2.sup.4                                                                           2.sup.3                                                                          2.sup.2                                                                          2.sup.1                                                                          2.sup.0                                     __________________________________________________________________________    I.sub.i < I.sub.D                                                                   0  6400                                                                              3200                                                                              1600                                                                              800 400                                                                              200                                                                              100                                                                              50                                          I.sub.i  -> I.sub.D                                                                 1  102400                                                                            51200                                                                             25600                                                                             12800                                                                             6400                                                                             3200                                                                             1600                                                                             800                                         ε × 100 (%)                                                              0.39                                                                              0.78                                                                              1.57                                                                              3.13                                                                              6.25                                                                             12.5                                                                             25 50                                          __________________________________________________________________________

It will be seen from Table 4 that I_(D) is preferably selected to beI_(D) = 12800 A, and the number of bits required for the AD converter inthis case is q+ 1= 9 bits including the weight bit WB. It is thusapparent that the number of required bits is less by three bits thanthat in the successive approximation type in which twelve bits arerequired. This verifies the effectiveness of the AD converter employedin the equipment according to the present invention.

Referring to FIG. 9, an analog input is applied to an input terminal Aof the AD converter, and after the period of time required forconversion, a digital output of (q+ 1) bits corresponding to the levelof the analog input appears at a plurality of terminals at the outputend DO of the AD converter. The structure and operation of this ADconverter will be described in more detail with reference to FIG. 9.

Flip-flops FF₇ to FF₀ are arranged to correspond to the weights ofindividual bits and are set successively in the above order in responseto the application of timing clock pulses from a pulse distributingcircuit PD. The flip-flops FF₇ to FF₀ control associated switching meansSW₇ to SW₀ and weight generating means W₇ to W₀ respectively so that thevoltage of a reference voltage source (V₁ or V₂) can be applied or notapplied to the weight generating means W₇ to W₀ depending on the stateof the respective flip-flops FF₇ to FF₀. These voltage values are thenadded together in an analog adder means Σ to obtain an output voltageE.sub.Σ which is compared in a comparator COM with an input voltageE_(i) applied to the input terminal A of the AD converter. When E_(i) ≧E.sub.Σ , the output of the comparator COM is "1" and the flip-flops FF₇to FF₀ remain in the set position, while when E_(i) < E.sub.Σ , theoutput of the comparator COM is "0" and the flip-flops FF₇ to FF₀ arereset in response to the application of the next timing clock pulses.The above operation is repeated by the number of bits according to theorder of from the largest weight to the smallest weight. (In the case ofconversion into a binary number, precision of (1/2^(q)) is obtained withrepetition of q times). When the above operation is repeated q times,that is, when one cycle is completed, the output values of theindividual flip-flops FF₇ to FF₀ represent the AD converted output DO(2⁷ to 2⁰). INHIBIT gates G₇ to G₀ in FIG. 9 control the application ofreset pulses to the respective flip-flops FF₇ to FF₀. For example, thesegates G₇ to G₀ inhibit passage of the reset pulses when the output ofthe comparator COM is "1" and allow for passage of the reset pulses whenthe output of the comparator COM is "0" .

The operation of the AD converter shown in FIG. 9 will be described inmore detail. The pulse distributing circuit PD generate successivetiming clock pulses CP₀ to CP₉. An output appears at the terminal Q or Qof each of the flip-flops FF₇ to FF₀ when a set pulse or reset pulse isapplied to the terminal S or R thereof. The INHIBIT gates G₀ to G₇control the application of the reset pulses to the associated flip-flopsFF₀ to FF₇. The reference voltage source V₁ is used when the relationbetween the input E_(i) and an intermediate reference voltage E_(D) isgiven by E_(i) ≧ E_(D). The reference voltage source V₂ is used when therelation between E_(i) and E_(D) is given by E_(i) < E_(D). E_(i)corresponds to I_(i) described previously. The switching means SW₀ toSW₇ control the application of the reference voltage of the referencevoltage source V₁ or V₂ to the weight generating means W₀ to W₇depending on the output of the flip-flops FF₀ to FF₇. The weightgenerating means W₀ to W₇ generate corresponding weights in response tothe application of the reference voltage from the reference voltagesource V₁ or V₂. The analog adder means Σ add the outputs of the weightgenerating means W₀ to W₇ to provide the output E.sub.Σ . The comparatorCOM compares the analog input E_(i) applied to the input terminal A ofthe AD converter with the output E.sub.Σ of the analog adder means Σ todeliver "1" when E₁ ≧ E.sub.Σ and "0" when E_(i) < E.sub.Σ . An AND gateGW₁ allows for passage of the timing clock pulse CP₁ only when therelation E_(i) ≧ E_(D) holds as a result of comparison between E_(i) andE_(D) immediately after the AD conversion is started. An INHIBIT gateGW₂ allows for passage of the timing clock pulse CP₁ only when therelation E_(i) < E_(D) holds. Two OR gates OG₁ and OG₂ are connected tothe set and reset terminals S and R respectively of the flip-flop FF₄ asshown. A flip-flop FF_(W) acts as a weight bit memory. The digitaloutput of the AD converter appears at the output end DO. Especiallynotable parts of the AD converter shown in FIG. 9 are the OR gates OG₁and OG₂ for controlling the determination of the weight bit WB, theflip-flop FF_(W) for memorizing the determined weight bit WB, and thetwo reference voltage sources V₁ and V₂ selectively used depending onthe output of the flip-flop FF_(W). The remaining parts of the ADconverter may be substantially similar to those commonly employed in theart and the function thereof is as described above.

The AD converter shown in FIG. 9 is featured by the fact that the levelof the analog input E_(i) is compared with the intermediate referencevoltage E_(D) computed on the basis of the allowable error of the systemin response to the application of the timing clock pulse CP₀ to theflip-flop FF₄ from the pulse distributing circuit PD at the beginning ofthe AD conversion, one of the reference voltage sources V₁ and V₂ isselected by the flip-flop FF_(W) depending on whether E_(i) is larger orsmaller than E_(D) and the individual bits are quantized by differentweights depending on the relation between E_(i) and E_(D). Therefore,the operation of the AD converter will be described while placingemphasis on these parts.

As described previously, the AD converter shown in FIG. 9 is designed tosuit the bit arrangement shown in Table 4. Thus, the intermediatereference voltage E_(D) is selected to correspond to the bit position2⁴. Therefore, the timing clock pulse CP₀ appearing at the beginning ofthe AD conversion passes through the OR gate OG₁ to be applied to theflip-flop FF₄ corresponding to the specific weight above described. Theswitching means SW₄ is closed and the output voltage E_(D) of thereference voltage source V₁ is applied through the switching means SW₄to the weight generating means W₄ so that the output E.sub.Σ of theanalog adder means Σ at this time is the output voltage E_(D) of theweight generating means W₄. The reference voltage source V₁ can be usedinitially due to the fact that the flip-flop FF_(W) is placed in the setposition by an instruction signal applied from a circuit (not shown)each time the AD conversion is started. Further, all the flip-flops FF₀to FF₇ are placed in the reset position by the circuit (not shown) eachtime the AD conversion is started.

The comparator COM compares the output E.sub.Σ = E_(D) of the analogadder means Σ with the input E_(i) applied to the input terminal A anddelivers an output of "1" level when, for example, E_(i) ≧ E.sub.Σ . Asa result, the AND gate GW₁ is opened to allow for passage of the nexttiming clock pulse CP₁ so that the flip-flop FF_(W) continues to bemaintained in the set position. Thus, the reference voltage source V₁can be used for the subsequent AD converting operation.

On the other hand, when E_(i) > E.sub.Σ , the comparator COM delivers anoutput of "0" level and the INHIBIT gate GW₂ is opened to allow forpassage of the timing clock pulse CP₁ thereby resetting the flip-flopFF_(W). In this case, the reference voltage source V₂ can be used forthe subsequent AD converting operation.

It is thus apparent that the weight for quantizing the input E_(i) canbe determined at the beginning of the AD conversion by the AD converterwhich is one of the features of the present invention. After thedetermination of the weight for quantizing the input E_(i), the timingclock pulse CP₁ is applied through the OR gate OG₂ to the reset terminalR of the flip-flop FF₄, and at the same time, to the set terminal S ofthe flip-flop FF₇ for generating the instruction signal for the greatestweight. It will be easily understood that this can be attained in theentirely same manner as that described briefly with reference to the ADconversion of successive approximation type. Upon completion of theconversion of all the bits, the outputs of the individual flip-flopsFF_(W), FF₇, FF₆, . . . FF₁, FF₀ appear as the output of the ADconverter.

Therefore, when the AD converter having a structure and function asshown in FIG. 9 is used in the coding equipment according to the presentinvention, the present invention may be applied to the bit positions 2⁰to 2⁷ of the output DO in FIG. 9, and at the same time, the weight bitWB may form an element of the weight character WC. In this case, it ispreferable that the weight bit WB is handled as an entirely independentelement as shown in FIG. 10 and the serial digital signal may have aform as shown in FIG. 11. FIGS. 10 and 11 correspond to FIGS. 3 and 2respectively and illustrate the case in which the AD converter of thetype shown in FIG. 9 is employed in the coding equipment of the presentinvention. As mentioned above, it is possible to reduce the necessarynumber of bits of each output code for keeping the possible error of theoutput within a predetermined allowable value by use of the A-Dconverter as shown in FIG. 9 compared with the number of bits as beingnecessary for assuring the same error when the inputs are applied to thecircuit as shown in FIG. 3. FIG. 10 shows a block diagram of anembodiment in which the inputs undergo discrimination by a circuit asshown in FIG. 9 as to whether the respective values of the inputs aregreater than the predetermined value I_(D) or not.

We claim:
 1. A coding equipment for encoding a physical quantity comprising analog-digital converting means for converting the physical quantity to a digital code signal, said analog-digital converting means including discriminator means having comparator means for discriminating whether the physical quantity is larger than a predetermined value or not, selecting means for selecting one of a plurality of predetermined different reference values in accordance with the output of said discriminating means, means for determining a weight for the digits of the digital code signal, said comparator means comparing the physical quantity with a value which is a function of the selected reference value and a weight which is predetermined depending on the position of each of the digits constituting the digital code signal, and compressing means for determining the position of the most significant digit in said digital code signal and for compressing said digital code signal in dependence on the position of the most significant digit in said digital code signal.
 2. A coding equipment according to claim 1, wherein said compressing means produces a train of codes including a code indicative of the position of the most significant digit and a predetermined number of digits succeeding the most significant digit.
 3. A coding equipment according to claim 2, further comprising means for generating a parity bit and a synchronizing signal for the train of codes of said compressing means.
 4. A coding equipment comprising:analog-digital converting means includinga plurality of first flip-flop means arranged in a predetermined order and having first and second input terminals, each of said flip-flop means being initially at a first state and changeable to a second state from the first state in response to a pulse signal applied to its first input terminal, said first flip-flop means being changeable to the first state from the second state in response to a pulse signal applied to its second input terminal, a plurality of switch means, each of said switch means being coupled to a respective one of said first flip-flop means and being responsive to the second state of the respective first flip-flop means for being rendered operative to permit an input signal applied thereto to pass therethrough, a plurality of weighting means, each of said weighting means being coupled to a respective one of said switching means for receiving the signal passed through the respective switching means and producing an output which is a function of the signal and a weight predetermined for said weighting means, adder means for producing an output corresponding to the sum of the outputs of said weighting means, comparator means for comparing the output of said adder means with a physical quantity to be coded and for producing a signal of a first level when said physical quantity is not less than the output of said adder means and a signal of second level when said physical quantity is less than the output of said adder means, second flip-flop means having first and second input terminals, said second flip-flop means being initially at a first state and changeable from the first to a second state in response to a pulse signal applied to its second input terminal, said second flip-flop means being changeable from the second state to the first state in response to a pulse signal applied to its first input terminal, means for applying to each of said switching means, as the input signal thereto, a first reference signal indicative to a first reference value when said second flip-flop means is at the first state and a second reference signal indicative of a second reference value when said second flip-flop means is at the second state, pulse distributing means for producing a plurality of signals in a predetermined order and in a predetermined timing, said pulse distributing means applying the first pulse signal to the first input terminal of a predetermined one of said plurality of first flip-flop means and applying the second pulse signal to the first input terminal of the first of the predetermined arrangement of said first flip-flop means and the second input terminal of said predetermined one of said first flip-flop means, said pulse distributing means applying the third and succeeding pulse signals to the first input terminals of the second and succeeding first flip-flop means, respectively, means for applying a pulse signal to the first input terminal of said second flip-flop means in response to said comparator means producing the first level signal and the second pulse signal of said pulse distributing means, and for applying a pulse signal to the second input terminal of said second flip-flop means in response to said comparator means producing the second level signal and said second pulse signal of said pulse distributing means, means for applying the third and successive pulse signals produced by said pulse distributing means to the second input terminal of the first flip-flop means in accordance with the second level signal being produced by said comparator means, and output means for producing a plurality of output signals indicative of whether respective ones of the plurality of first flip-flop means are at the first state or the second state and an output signal indicative of whether said second flip-flop means is at the first state or the second state; means for determining the position of the first flip-flop means in the first state corresponding to an output in the most significant digit position; encoding means for producing a code in dependence on the position of said determined first flip-flop means; gate means for permitting selected ones of said plurality of output signals from said output means, respectively, corresponding to a predetermined number of the first flip-flop means succeeding said determined first flip-flop means to pass therethrough; and means responsive to at least the code produced by said encoding means and said selected output signals of said output means for producing a train of codes. 